wafer.space Community - Improving bandgap line regulation

Any suggestions for how to improve line regulation at higher voltages?

That screenshot is way too poor to read anything

6:36 p.m.

Put the whole project up on a public repo

I'll clean it up then put it on a public repo. It's a little messy right now.

IIRC xschem lets you export at higher resolution (than whatever your screen can do) and/or vector graphics. Also at least just zoom in as much as your screen can handle onto each isolated (as far as wires in the schematic go) section and screenshot them individually.

Going to make a repo soon (edited)

10:25 p.m.

I just want to clean everything up. Doing this for Chipalooza #3

10:26 p.m.

I mainly wanted to see if there was anything topologically that I could improve; I get good performance at 3v3 but not at 5V. I initially designed everything for 3v3 but then shifted to 5V

Jonah Saunders

Any suggestions for how to improve line regulation at higher voltages?

throw an LDO in front? Doesn't need to be very regulated I guess, just compress the range between "minimum operating voltage" and "maximum operating voltage" to a small fraction of what it would be without that LDO.

As for figuring out what's becoming more sensitive/infuential as voltage goes up, ..... WHY is your vref pnp branch lacking the XM4/XM3 equivalent? Also beware that you're doing.... well, I mean, it's obviously substantially different, but why is yours "better"?: https://en.wikipedia.org/wiki/Brokaw_bandgap_reference At least regarding that you have base collector shorted on your pnp's and the linked has all 3 terminals of each one of the two npn's it has at different voltages.

Brokaw bandgap reference

The Brokaw bandgap reference is a voltage reference circuit widely used in integrated circuits, with an output voltage around 1.25 V that exhibits low temperature dependence. This particular circuit is one type of a bandgap voltage reference, named after Paul Brokaw, the author of its first publication. Like all temperature-independent bandgap ...

I followed this paper.

Systematic_Design_of_Bandgap_Voltage_Reference_Using_Precomputed_Lookup_Tables.pdf

7.03 MB

you can use the sensitivity analysis of your SPICE to apply the tuning some more btw....

11:28 p.m.

like, without deference to those LUTs

I used gm/id for the entire project

but yeah, for improving PSRR, active filter in front to limit the input voltage to more limited range should help a lot.> if you make that one start up transparent/pass-active it should do great. Consider using the native NMOS for that actually, like, with a pull-up resistor from gate to drain, and once the vref is active, you can compare a resistor division of the LDO output against vref and pull the gate down if the resistor division is too high (relatively).

Jonah Saunders

I used gm/id for the entire project

oh yeah ..... yeahhhhhhh...... those devices are only first order gm/id. Especially not across PVT.

11:33 p.m.

But: it's already looking decent.

Yeah with resistor trimming performance is quite good. The line regulation and PSRR just isn't amazing

And I think the paper describes in enough detail how to do an optimization loop based on the circuit simulation/model to iteratively hunt for the perfect device sizing.

Jonah Saunders

Yeah with resistor trimming performance is quite good. The line regulation and PSRR just isn't amazing

Yeah if ngspice or Xyce 's sensitivity modes can express the line regulation and PSRR (I think those would be small signal AC analysis under whichever applicable bias conditions; and IIRC at least Xyce's AC sensitivities should cover that, though it will do some numerical differentiating I think due to not yet having algebraic matrix derivatives yet), you should be able to take the parts of the circuit under inspection and apply the iterative optimization of the paper, or even just let some trust region optimizer go to town tasked with line regulation and PSRR while you enforce the zero/neutral tempco and cap the maximal tempco at extremes.

Got it fixed by using 2 more cascodes

5:15 p.m.

do consider using spare area over the bandgap on MIM decoupling capacitors btw.

namibj

do consider using spare area over the bandgap on MIM decoupling capacitors btw.

The PSRR performance is so bad at high frequencies without the MIM caps

Jonah Saunders

The PSRR performance is so bad at high frequencies without the MIM caps

Remember you ideally want to apply several MHz of VDD with negated polarity to vref with strength adjusted to cancel capacitive divider action. I'm presuming this would look like a few poly resistors and a few thin oxide NMOS that are wired like a current mirror to give simple high bandwidth compensation that the poly resistors can tune to approximate the amount of STATISTICALLY EXPECTED stray capacitance coupling of non-negated VDD into vref. Btw, make sure to use drain-side-salicyde-block (DSS) transistors for that; use very short channels to minimize their own capacitance so that this on it's own works up to frequencies high enough that the iirc thermal white noise dominates over the power supply noise, remember the eventual no longer inverted cancellation feed gets dominated by the MIM caps if you do it at high enough frequency. Btw; I haven't read the gf180mcuD Chipalooza details but if it's close enough to the IHP in harness architecture I suggest you use a comfortably large thick oxide NMOS pass-transistor driven by a tiny transistors digital inverter (if you have digital stuff should be fine to just force instantiate a plain single-strength inverter; else I'd suggest to manually assemble one flanked by a full tap cell on one side and row end cells at the outside of this inverter w/ tap cell "row"; if you'd need help I could probably whip it up in Klayout real quick some time soon; though thinking now you could probably just stick to consuming the harness pin directly and not have your own CMOS inverter at all) with a small poly resistor between the digital inverter and the sizable thick oxide NMOS to "RC filter" digital VDD&VSS a bit. Then using the sizable thick oxide NMOS to select if the "bonus" big MIM cap filling spare area of your slot is made use of or if it's disconnected, as I think your bandgap won't be nearly as huge as the entire slot you're allocated, so being able to easily prove measured performance both for the small self-contained variant and for the larger full slot approach should be quite useful IMO.

Mhm that is really good advice. Currently cleaning up the entire repo and testbenches to make it less of a mess.

I think it might be insightful to view power supply noise influence as magnitude and phase (ideally continuos phase if that's available, as broadband mitigation through interference [the same thing differential circuits do to get their common mode rejection: ensure half of the signal (or the interference, which doesn't matter they chose signal you choose interference) adds with the interference while being opposite polarity, so that overall the interference cancels out] care about matching group delay between the signal and the compensating path (and having the polarity as desired) instead of trickery with delaying signal to get that 180 degree of phase). Then look at how large that is at various nodes in the schematic.